Advanced VHDL for FPGA
This training is intended to professional who already knows how to use programmable components but also have to create and test them; it is intended to complement the course VHDL Language Basics.
Advanced VHDL for FPGA
– Acquire a strong design methodology with the best of VHDL for simulation and synthesis
Objectives
Comprehend the various possibilities offered by VHDL language
Be able to read and test VHDL components
Understand the logical synthesis notions
Understand the crucial issue of implementing Finite State Machines (FSMs) in hardware
Reusing components
Checking Timings
The OSVVM and UVVM VHDL verification methodologies
Prerequisites
Basic knowledge of VHDL, VHDL Language Basics course level 1
Target Audience
Any embedded systems engineer or technician with the above prerequisites
Day One
Finite State Machine (1st part)
The Finite State Machine Approach
Sequential Circuits and State Machines
State Transition Diagram
Transition Types
Moore-to-Mealy Conversion
Mealy-to-Moore Conversion
Exercises
Hardware Fundamentals
Flip-Flops
Metastability and Synchronizers
Pulse Detection
Glitches
Pipelined Implementations
Exercises
Hardware Architectures for State Machines
Fundamental Design Technique for Moore Machines
Fundamental Design Technique for Mealy Machines
Moore versus Mealy Time Behavior
State Machine Categories and State-Encoding Options
Safe State Machines
Finite State Machine (2nd part)
Design Steps and Classical Mistakes
Classical Problems and Mistakes
Design Steps Summary
Regular State Machines
Architectures for Regular Machines
Number of Flip-Flops
Exercises
Timed State Machines
Architectures for Timed Machines
Timer interpretation
Transition Types and Timer Usage
Timer Control Strategies
Time Behavior of Timed Moore and Mealy Machines
Examples of Timed Machines
Exercise: | Designing a burstable RAM controller |
Day Two
Design Methodology for Synthesis
Designing for Synthesis
Metastability
Memory Synthesis
Reset Generation
Crossing Clock domains
Exercise: | Metastability |
Timing analysis and constraints
Timing Closure challenges
A methodology for successful Timing Closure
Common Timing Closure Issues
Static Timing Analysis
Role of Timing Constraints in STA
Common Issues in STA
Delay Calculation versus STA
Timing Path
Setup and Hold
Slack
On-Chip Variation
Clock
Port Delays
Completing Port Constraints
False Paths
Multi Cycle Paths
Combinational Paths
Xilinx Extensions
Exercise: | Design closure |
Exercise: | Analyzing and Resolving timing violations |
Day Three
Introduction to Open Source VHDL Verification Methodology (OSVVM)
Overview
Transaction-Level Modeling
Constrained Random Test Generation
Functional Coverage
Intelligent Coverage Randomization Methodology
Utilities for Testbench Process Synchronization
Transcript Files
Error Logging and Reporting: Alerts and Affirmations
Introduction to Universal VHDL Verification Methodology (UVVM)
Utility Library
VVC (VHDL Verification Component) Framework
BFMs (Bus Functional Models
OSVVM and UVVM
Vivado Debug
Vivado Integrated Logic Analyzer (ILA)
Adding debug nets
Analyzing debug data
Resources
Nohau Training Partner
This course is provided by a Nohau Training Partner, a trusted provider of hands-on training for professionals in embedded systems, software development, and engineering.
